1. Technical Field
The disclosed embodiments relate to sense amplifiers and global read line architectures in multi-bank semiconductor memories.
2. Background Information
FIG. 1 (Prior Art) is a diagram of a multi-bank memory structure that employs a shared sense amplifier output architecture. For example, data being read out of BANK0 and data being read out of BANK1 both pass through the same sense amplifier 1. Sense amplifier 1 is therefore said to be “shared” between the two banks. Each sense amplifier of FIG. 1 drives a common single-ended global read line (RD) 2 using a tri-state driver. Tri-state driver 3 is the driver for sense amplifier 1. In operation, the output leads of all the tri-state drivers are coupled to the global read line 2 as illustrated. On every memory access, the global read line 2 is driven by one of the tri-state drivers. All others of the tri-state drivers in their high impedance states and are isolated from global read line 2. Global read line 2 is either driven high or low depending on the value of the data being output. The data is driven through the sense amplifier, through the enabled tri-state driver, through the global read line 2, through an output buffer 4, and from the memory. The column of banks and the associated sense amplifiers and tri-state drivers can be replicated such that there are multiple such columns, and such that the tri-state drivers of the various columns all drive the same global read line 2. Similarly, the number of banks in each column can be increased as long as the tri-state drivers of each bank are coupled to the global read line.
The shared architecture of FIG. 1 has several advantages as compared to a non-shared sense amplifier scheme. First, the number of sense amplifiers is halved as compared to the number of banks. By reducing the number of sense amplifiers due to sharing, the amount of integrated circuit area consumed is reduced. Second, device junction capacitance on each global read line is reduced. Rather than having two tri-state drivers coupled to the global read line for each pair of banks, there is only one tri-state driver coupled to the global read line for each pair of banks.
The shared structure of FIG. 1, however, has a disadvantage in that there can be considerable capacitive loading on the input leads of the sense amplifiers. Assume that P-channel transistors 5 were not present. Assume that the column read/write multiplexers are four-to-one multiplexers. Assume that a sense amplifier is shared between two banks as illustrated. In such a situation, there would be eight N-channel transistors coupled to each sense amplifier input lead. Each of these N-channel transistors has a device junction capacitance. The corresponding large amount of capacitance on the input lead of the sense amplifier would slow the data output signal path significantly. To reduce this capacitance, P-channel transistors 5 are sometimes added. P-channel transistors 5 isolate device junction capacitance of the column read/write multiplexers from one another. Unfortunately, placing the P-channel transistors 5 in the data output signal path reduces memory readout speed.
In addition to slowing memory read out speed due to isolating P-channel transistors 5, the shared structure of FIG. 1 involves an undesirable amount of capacitive loading on global read line 2. In the structure of FIG. 1, each tri-state driver involves one N-channel transistor coupled to global read line 2 and one P-channel transistor coupled to global read line 2. Due to the lower mobility of holes than electrons, the P-channel transistor is generally approximately twice as large as the N-channel transistor. The two transistor size units of a P-channel transistor is denoted “2X” in FIG. 1, whereas the one transistor size unit of an N-channel transistor is denoted “1X” in FIG. 1. The size of the transistor has a primary impact on the capacitance added onto the global read line 2 by the transistor. Each such tri-state driver therefore adds approximately three transistor size units of capacitive loading to global read line 2. There are two transistor size units for the P-channel pullup transistor and one transistor size unit for the N-channel pulldown transistor. For an example of four banks, the global read line 2 is loaded with six transistor-size units. This large capacitive loading on the global read line has an undesirable impact on memory readout time.
FIG. 2 (Prior Art) is a diagram of a multi-bank memory structure that employs a non-shared sense amplifier output architecture. There is one sense amplifier for each bank. Rather than using tri-state output drivers to drive a single global read line to either a digital logic high level or a digital logic low level, there are two global read lines. Each global read line 6 and 7 of the non-shared structure of FIG. 2 is only pulled down when data is read out of the memory. The global read lines 6 and 7 are initially precharged to the same voltage by precharge circuitry 8. Precharage circuitry 8 is then disabled. If, for example, the RBIT value being read out of BANKN-1 is a digital logic high and the RBITB value being read out of BANKN-1 is a digital logic low, then pulldown transistor 9 is nonconductive and the pulldown transistor 10 is conductive. Global read line RD is therefore not pulled down but rather stays at its precharged voltage. Global read line RDB, however, is pulled down by transistor 10. The voltage differential between the global read lines 6 and 7 is converted by output buffer 11 into a corresponding digital logic high value that is output onto data output lead 12. If, on the other hand, the RBIT value being read out of BANKN-1 is a digital logic low and the RBITB value being read out of BANKN-1 is a digital logic high, then pulldown transistor 9 is conductive and pulldown transistor 10 is nonconductive. Global read line RD is therefore pulled down toward ground potential by transistor 9. Global read line RDB, however, stays at its precharged voltage. The voltage differential between global read lines 6 and 7 is converted by output buffer 11 into a corresponding digital logic low value on data output lead 12.
The non-shared structure of FIG. 2 has several advantages as compared to the shared structure of FIG. 1. First, because each sense amplifier only receives data from one column read/write multiplexer, the P-channel isolating transistors 5 of FIG. 1 are not provided. This speeds memory readout. Second, the non-shared structure of FIG. 2 has a smaller amount of capacitive loading on the global read lines 6 and 7. In the structure of FIG. 2, for an example of four banks, there are four N-channel pulldown transistors coupled to each the global read line. Each N-channel pulldown transistors is designated in FIG. 2 to involve one transistor size unit of capacitive loading. This one transistor size unit is designated “1X”. The precharge circuitry 8 adds some capacitance to the global read lines but there is only one such circuit 8 for each column of banks so the added capacitive loading is relatively small where there are many banks. As can be seen from FIG. 2, the loading of four transistor size units on each global read line of FIG. 2 is better than the loading of six transistor size units of FIG. 1.
Unfortunately, the non-shared structure of FIG. 2 has a disadvantage. The non-shared structure of FIG. 2 involves twice as many sense amplifiers as compared to the shared structure of FIG. 1. In the shared structure of FIG. 1 where there are four banks, only two sense amplifiers are required. In the non-shared structure of FIG. 2 where there are four banks, however, four sense amplifiers are required.